1. Field of the Invention
This invention relates to a driver, and more particularly to a light emitting diode driver.
2. Description of the Related Art
Referring to FIGS. 1 and 2, a first conventional light emitting diode (LED) driver 1 is shown to generate sixteen driving current signals, which are used to respectively drive sixteen light emitting units 2. Each of the light emitting units 2 may include at least one LED 21. FIG. 1 shows an example, in which each of the light emitting units 2 includes only one LED 21. The first conventional LED driver 1 includes a serial-to-parallel conversion unit 11, a data buffer unit 12, and an output unit 13.
The serial-to-parallel conversion unit 11 receives a reference clock signal, and a serial input signal carrying sixteen 16-bit gray codes. The serial-to-parallel conversion unit 11 is operable to convert, based on the reference clock signal, the serial input signal into a parallel input signal carrying the 16-bit gray codes. All sixteen ith bits of all of the 16-bit gray codes are converted at a time, where 1≦i≦16. Therefore, sixteen conversion operations are required for generation of the parallel input signal.
The data buffer unit 12 has a storage capacity of 16 bits. The data buffer unit 12 is coupled to the serial-to-parallel conversion unit 11 for receiving the parallel input signal therefrom, and further receives a latch signal. The data buffer unit 12 is operable to store, based on the latch signal, the sixteen ith bits of all of the 16-bit gray codes carried by the parallel input signal.
The output unit 13 is coupled to the data buffer unit 12 for receiving the bits stored thereby, and further receives an output control signal. During each cycle (T1), the output control signal non-periodically changes between a logic low level and a logic high level, and non-duty cycles of the output control signal during which the output control signal is at the logic low level gradually increase by a geometric sequence with a common ratio of 2. That is to say, the non-duty cycles sequentially are T, 2T, 4T, 8T, . . . , and 215T. The output unit 13 is operable to generate the driving current signals based on the output control signal and the bits, such that each of the driving current signals has a current value, which is determined based on a respective one of the bits to be a predetermined current value (if the respective one of the bits is ‘1’) or zero (if the respective one of the bits is ‘0’) when the output control signal is at the logic low level, and which is zero when the output control signal is at the logic high level.
The current value of each driving current signal is determined based on the ith bit of a respective 16-bit gray code within a duration of 2i-1T. Accordingly, an average luminance of each light emitting unit 2 is proportional to a gray value represented by the respective 16-bit gray code.
However, since the data buffer unit 12 stores only sixteen bits to be used at a time, a time period between any two adjacent ones of falling edges of the output control signal (e.g., the time period (T2) between first and second falling edges of the output control signal) must be sufficient to serially input sixteen bits to the serial-to-parallel conversion unit 11. Therefore, the first conventional LED driver 1 is disadvantageous in that a refresh rate (i.e., 1/T1) of each driving current signal is limited by a rate at which the bits are inputted to the serial-to-parallel conversion unit 11.
Referring to FIGS. 3 and 4, a second conventional LED driver 3 is shown to generate sixteen driving current signals, which are used to respectively drive sixteen light emitting units 4. Each of the light emitting units 4 may include at least one LED 41. FIG. 3 shows an example, in which each of the light emitting units 4 includes two LEDs 41. The second conventional LED driver 3 includes a serial-to-parallel conversion unit 31, a data buffer unit 32, a control unit 33, and an output unit 34.
The serial-to-parallel conversion unit 31 receives a reference clock signal, and a serial input signal carrying sixteen 16-bit gray codes. The serial-to-parallel conversion unit 31 is operable to convert, based on the reference clock signal, the serial input signal into a parallel input signal carrying the 16-bit gray codes.
The data buffer unit 32 has a storage capacity of 16×16 bits. The data buffer unit 32 is coupled to the serial-to-parallel conversion unit 31 for receiving the parallel input signal therefrom, and further receives a latch signal. The data buffer unit 32 is operable to store, based on the latch signal, the 16-bit gray codes carried by the parallel input signal.
The control unit 33 is coupled to the data buffer unit 32 for receiving the 16-bit gray codes stored thereby, and further receives an output control signal. The output control signal periodically changes between a logic low level and a logic high level by a predetermined frequency (i.e., 1/T) during each cycle. The control unit 33 is operable to generate sixteen pulse width control signals, each of which is generated based on the output control signal and a respective one of the 16-bit gray codes.
The output unit 34 is coupled to the control unit 33 for receiving the pulse width control signals therefrom, and further receives the output control signal. The output unit 34 is operable to generate the driving current signals based on the output control signal and the pulse width control signals such that each of the driving current signals has pulse widths (T1-T64), which are determined based on the output control signal and a respective one of the pulse width control signals. A sum of the pulse widths (T1-T64) of each of the driving current signals during each cycle of the output control signal (i. e., T1+T2+ . . . +T64) is proportional to a gray value represented by a respective one of the 16-bit gray codes. Therefore, an average luminance of each of the light emitting units 2 is proportional to the gray value represented by the respective one of the 16-bit gray codes.
Since the data buffer unit 32 can pre-store the 16-bit gray codes to be used, an interval waiting time for serially inputting the 16-bit gray codes to the serial-to-parallel conversion unit 31 can be reduced. Therefore, a refresh rate of each of the driving current signals of the second conventional LED driver 3 can be raised compared to that of the first conventional LED driver 1 of FIG. 1.
However, the control unit 33 required to control the pulse widths of each of the driving current signals is relatively complex. Therefore, the second conventional LED driver 3 disadvantageously has a relatively high cost.